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Benny Åkesson (Publications)

Benny Åkesson (Publications)

Benny Åkesson (Publications)

PhD Eindhoven University of Technology, Netherlands
Collaborator PhD Researcher

Benny Akesson received his MSc degree at Lund Institute of Technology, Sweden in 2005 and a PhD from Eindhoven University of Technology, the Netherlands in 2010. Since then, he has been employed as a Researcher at Eindhoven University of Technology, Czech Technical University in Prague, and CISTER/INESC TEC Research Unit in Porto. He is a Professor by Special Appointment at the University of Amsterdam and holds the Chair of Design Methodologies for Cyber-physical systems since 2019.

Currently, Prof. Akesson is working as a Senior Research Fellow at ESI (TNO) in Eindhoven. His research interest is design methodologies for cyber-physical systems, in particular model-based engineering and real-time systems. He has published more than 60 peer-reviewed conference papers and journal articles, as well as two books about memory controllers for real-time embedded systems.

Benny was in CISTER from August 2012 - January 2013 and returned to the unit in July 2015.

 

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Journal Papers
Time-Triggered Co-Scheduling of Computation and Communication with Jitter Requirements CISTER-TR-170702 
Anna Minaeva, Benny Åkesson, Zdeněk Hanzálek, Dakshina Dasari
ABSTRACT Additional Files: PDFOpen Access Version
IEEE Transactions on Computers, IEEE. 1, Jan, 2018, Volume 67, Issue 1, pp 115-129.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact) CISTER-TR-181107 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDagstuhl Artifacts Series (DARTS), Article No 5, Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. 2018, Volume 4, Issue 2, pp 5:1-5:3.
Conference or Workshop Papers/Talks
Decoupling Criticality and Importance in Mixed-Criticality Scheduling CISTER-TR-181119 
Konstantinos Bletsas, Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Alan Burns, Eduardo Tovar6th International Workshop on Mixed Criticality Systems (WMC 2018). 11, Dec, 2018, pp 25-30. Nashville, U.S.A..WMC 2018 was held as part of RTSS 2018, Nashville, USA, 11-14 December.
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers CISTER-TR-180401 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.Volume 106
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018, pp 1277-1282. Dresden, Germany.
Technical Reports
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation (Long Version) CISTER-TR-180603 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.