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Muhammad Ali Awan (Publications)

Muhammad Ali Awan (Publications)

Muhammad Ali Awan (Publications)

PhD University of Porto, Portugal
Integrated Researcher

Muhammad Ali Awan received his Bachelors Degree in Computer Engineering from National University of Science and Technology (NUST) Pakistan in 2005. He completed his Master's Degree in 2007 from Royal Institute of Technology(KTH) Sweden in System on Chip Design with a focus on Digital System Design and Embedded Systems. He worked as Lecturer in NUST from 2007 to 2008. Afterwards, he joined IMEC Belgium as a researcher for two years and focused on High Level Memory Management issues.

He joined CISTER Research Center in 2010 and enrolled as a PhD candidate in University of Porto Portugal. During his four years of PhD program, he participated in a research on "Real-Time Power Management on Partitioned Multicores". His research interests include real-time scheduling theory, energy-aware scheduling, heterogeneous multicore architecture design and exploration, low-power digital design and system-on-chip design methodology and resource-aware system optimizations.

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Conference or Workshop Papers
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018. Hakodate, Japan.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers CISTER-TR-180401 
Muhammad Ali Awan, Pedro F. Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201 
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018. Dresden, Germany.
Technical Reports
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation (Long Version) CISTER-TR-180603 
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.