Konstantinos Bletsas (Publications)
PhD University of York, United Kingdom
Integrated PhD Researcher
Integrated PhD Researcher
Konstantinos Bletsas (born in 1978 in Greece) has a Degree in Electronic and Computer Engineering (2002) from the Technical University of Crete (Chania, Greece) and a PhD in Computer Science (2007) from the University of York (UK). He joined the CISTER research unit in 2007. His main research focus is on multiprocessor and/or mixed-criticality scheduling algorithms and their timing analysis. He is currently serving as Associate Editor for "Real-Time Systems", the flagship journal in the area, and has also served the technical program committees of top-impact conferences in the core real time area, such as ECRTS (2013, 2014, 2015, 2016, 2021), IEEE RTAS (2016), RTCSA (2018, 2019) and RTSS (2017, 2019, 2022). He has also supervised one completed PhD.
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Journal Papers
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers (Artifact) CISTER-TR-181107
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDagstuhl Artifacts Series (DARTS), Article No 5, Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. 2018, Volume 4, Issue 2, pp 5:1-5:3.
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDagstuhl Artifacts Series (DARTS), Article No 5, Schloss Dagstuhl-Leibniz-Zentrum fuer Informatik. 2018, Volume 4, Issue 2, pp 5:1-5:3.
PDFErrata for Three Papers (2004-05) on Fixed-Priority Scheduling with Self-Suspensions CISTER-TR-181108
Konstantinos Bletsas, Neil Audsley, Wen-Hung Huang, Jian-Jia Chen, Geoffrey NelissenLeibniz Transactions on Embedded Systems (LITES), Article No 2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik, Dagstuhl Publishing, Germany. 2018, Volume 5, Issue 1, pp 02:1-02:20.
Konstantinos Bletsas, Neil Audsley, Wen-Hung Huang, Jian-Jia Chen, Geoffrey NelissenLeibniz Transactions on Embedded Systems (LITES), Article No 2, Schloss Dagstuhl – Leibniz-Zentrum für Informatik, Dagstuhl Publishing, Germany. 2018, Volume 5, Issue 1, pp 02:1-02:20.
Conference or Workshop Papers/Talks
Decoupling Criticality and Importance in Mixed-Criticality Scheduling CISTER-TR-181119
Konstantinos Bletsas, Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Alan Burns, Eduardo Tovar6th International Workshop on Mixed Criticality Systems (WMC 2018). 11, Dec, 2018, pp 25-30. Nashville, U.S.A..WMC 2018 was held as part of RTSS 2018, Nashville, USA, 11-14 December.
Konstantinos Bletsas, Muhammad Ali Awan, Pedro Souto, Benny Åkesson, Alan Burns, Eduardo Tovar6th International Workshop on Mixed Criticality Systems (WMC 2018). 11, Dec, 2018, pp 25-30. Nashville, U.S.A..WMC 2018 was held as part of RTSS 2018, Nashville, USA, 11-14 December.
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation CISTER-TR-180604
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar24th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2018). 28 to 31, Aug, 2018, Session 4: Support for Predictability, pp 111-117. Hakodate, Japan.
Worst-case Stall Analysis for Multicore Architectures with Two Memory Controllers CISTER-TR-180401
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.Volume 106
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo Tovar30th Euromicro Conference on Real-Time Systems (ECRTS 2018). 3 to 6, Jul, 2018, pp 2:1-2:22. Barcelona, Spain.Volume 106
Mixed-criticality Scheduling with Memory Bandwidth Regulation CISTER-TR-171201
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018, pp 1277-1282. Dresden, Germany.
Muhammad Ali Awan, Pedro Souto, Konstantinos Bletsas, Benny Åkesson, Eduardo TovarDesign, Automation and Test in Europe 2018 (DATE 2018). 19 to 23, Mar, 2018, pp 1277-1282. Dresden, Germany.
Technical Reports
Mixed-criticality Scheduling with Dynamic Memory Bandwidth Regulation (Long Version) CISTER-TR-180603
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.
Muhammad Ali Awan, Konstantinos Bletsas, Pedro Souto, Benny Åkesson, Eduardo Tovar28, Aug, 2018.
Linear modelling of Boolean functions CISTER-TR-181005
Kostiantyn Berezovskyi, Konstantinos Bletsas, Eduardo Tovar2018.
Kostiantyn Berezovskyi, Konstantinos Bletsas, Eduardo Tovar2018.