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Jatin Arora (Publications)

Jatin Arora (Publications)

Jatin Arora (Publications)

PhD University of Porto, Portugal

Jatin joined the CISTER research unit in September 2018 as a PhD student. He is currently an Integrated PhD Researcher at CISTER and Embedded Systems Research Scientist at VORTEX CoLab, where he is involved in cutting-edge research for the safety and security of cyber-physical systems.

He completed his PhD in Electrical and Computer Engineering from the Faculty of Engineering, University of Porto in 2023. His dissertation focused on the schedulability analysis of real-time tasks executing on COTS multicore systems by building novel solutions for accurately quantifying contention due to the sharing of main memory and memory buses in multicore platforms. His PhD research was partially funded by FCT (Portuguese Foundation for Science and Technology) under the individual PhD grant.

Before joining CISTER, he received M.Tech in Embedded Systems and B.Tech in Electronics & Communication Engineering from India in 2017 and 2014, respectively. He has co-authored several publications in reputed real-time systems conferences and journals. Among other awards and honors, he received the "Best Paper Award" at ICESS 2021 and "PhD Forum Prize" at DATE 2023.

His research interests encompass real-time embedded systems, timing and scheduling analysis, resource contention, and predictability in multicore architectures.

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Thesis
Shared Resource Contention-Aware Schedulability Analysis of Hard Real-Time Systems CISTER-TR-231001 
Jatin AroraPhD Thesis. 8, Sep, 2023. Porto.The PhD examination committee was composed of: President: Prof. José Nuno Moura Marques Fidalgo, Associate Professor at the Faculty of Engineering of the University of Porto, Portugal; Referee: Prof. Renato Mancuso, Assistant Professor in the Department of Computer Science at Boston University, USA; Referee: Prof. Isabelle Puaut, Full Professor at the University of Rennes, France; Referee: Prof. Pedro Alexandre Guimarães Lobo Ferreira Souto, Assistant Professor at the Faculty of Engineering of the University of Porto, Portugal; Supervisor: Prof. Eduardo Manuel Medicis Tovar, Director of the CISTER
Journal Papers
Schedulability Analysis for 3-Phase Tasks with Partitioned Fixed-Priority Scheduling CISTER-TR-220801 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarJournal of Systems Architecture (JSA), Elsevier. Oct 2022.
Bus-Contention Aware WCRT Analysis for the 3-Phase Task Model Considering a Work-Conserving Bus Arbitration Scheme CISTER-TR-211004 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo TovarJournal of Systems Architecture (JSA), Elsevier. 2022. (Best Paper of ICESS 2021) (ICESS 2021). 13 to 14, Jan, 2022, Volume Technical Session. Virtual, Australia.
Wearable Sensors Based Remote Patient Monitoring using IoT and Data Analytics CISTER-TR-191001 
Jatin Arora, Patrick Meumeu YomsiU.Porto Journal of Engineering, FEUP. 2019, Volume 5, Issue 1, pp 34-45.
Conference or Workshop Papers/Talks
Improved Bus Contention Analysis for 3-Phase Tasks CISTER-TR-230505 
Jatin Arora, Syed Aftab Rashid, Geoffrey Nelissen, Cláudio Maia, Eduardo Tovar29th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA 2023). 30, Aug to 1, Sep, 2023, Technical Session. TOKI MESSE, Niigata, Japan.The paper is accepted as a full paper in RTCSA 2023.
Memory Contention Analysis for 3-Phase Tasks CISTER-TR-230503 
Jatin Arora, Syed Aftab Rashid, Geoffrey Nelissen, Cláudio Maia, Eduardo TovarJunior Researcher Workshop on Real-Time Computing, co-located with RTNS 2023 (JRWRTC 2023). 7 to 8, Jun, 2023, Workshop session. Dortmund, Germany.
Shared Resource Contention Aware Schedulability Analysis for Multiprocessor Real-Time Systems CISTER-TR-221202 
Jatin Arora, Eduardo Tovar, Cláudio Maia
ABSTRACTPDFPDF Additional Files: PDFPoster
Design, Automation and Test in Europe Conference (DATE 2023). 17 to 19, Apr, 2023, PhD Forum. Antwerp, Belgium.
Work-in-Progress: A Holistic Approach to WCRT Analysis for Multicore Systems CISTER-TR-220907 
Jatin Arora, Syed Aftab Rashid, Cláudio Maia, Geoffrey Nelissen, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPoster
Work in Progress Session, 43rd Real-Time Systems Symposium (RTSS 2022). 5 to 8, Dec, 2022. Houston, Texas, U.S.A..
Analyzing Fixed Task Priority Based Memory Centric Scheduler for the 3-Phase Task Model CISTER-TR-220608 
Jatin Arora, Syed Aftab Rashid, Cláudio Maia, Eduardo TovarIEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA). 23 to 25, Aug, 2022, Technical Session. Taipei, Taiwan.
Open Questions for the Bus-Blocking Problem in the 3-Phase Task Model under Partitioned Scheduling CISTER-TR-210503 
Jatin Arora, Cláudio Maia, Syed Aftab RashidCAPITAL Workshop - sCalable And PrecIse Timing AnaLysis for multicore platforms (CAPITAL 2021). 4, Jun, 2021, Junior Presentations. Online.
Bus-Contention Aware Schedulability Analysis for the 3-Phase Task Model with Partitioned Scheduling CISTER-TR-210206 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar29th International Conference on Real-Time Networks and Systems (RTNS 2021). 7 to 9, Apr, 2021, Technical Session. Online.
Open Issues in Analyzing the Schedulability for the 3-Phase Task Model using Partitioned Scheduling CISTER-TR-210603 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Eduardo TovarThe symposium of “Electrical and Computer Engineering” of the 4th Doctoral Congress Engineering (DCE21) (DCE). 2021, Poster/Presentation Session. Online.
Work-In-Progress: WCRT Analysis for the 3-Phase Task Model in Partitioned Scheduling CISTER-TR-201005 
Jatin Arora, Cláudio Maia, Syed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar
ABSTRACTPDFPDF Additional Files: PDFPoster
Work in Progress Session, 41st IEEE Real-Time Systems Symposium (RTSS 2020). 1 to 4, Dec, 2020, pp 407-410. Online.