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Seminar Series 2020 - Ishfaq Hussain

Seminar Series 2020 - Ishfaq Hussain

Response Time Analysis of Multiframe Mixed Criticality Systems
3, Mar, 2020 11:30-12:30 (1 hour)
CISTER, Porto, Portugal

ABSTRACT:
The well-known model of Vestal aims to avoid excessive pessimism in the quantification of the processing requirements of mixed criticality systems, while still guaranteeing the timeliness of higher criticality functions. This can bring important savings in system costs, and indirectly help meet size, weight and power constraints. This efficiency is promoted via the use of multiple worst-case execution time (WCET) estimates for the same task, with each such estimate characterized by a confidence associated with a different criticality level. However, even this approach can be very pessimistic when the WCET of successive instances of the same task can vary greatly according to a known pattern, as in MP3 and MPEG codecs or the processing of ADVB video streams. In this talk, we present a schedulability analysis for the multiframe mixed-criticality model, which allows tasks to have multiple, periodically repeating, WCETs in the same mode of operation. Our work extends both the analysis techniques for Static Mixed-Cricality scheduling (SMC) and Adaptive Mixed-Criticality scheduling (AMC), on one hand, and the schedulability analysis for multiframe task systems on the other. Our proposed worst-case response time (WCRT) analysis for multiframe mixed-criticality systems is considerably less pessimistic than applying the SMC, AMC-rtb and AMC-max tests obliviously to the WCET variation patterns. Experimental evaluation with synthetic task sets demonstrates up to 63.8% higher scheduling success ratio (in absolute terms) compared to the best of the frame-oblivious tests.



BIO:
Ishfaq Hussain has obtained his Masters degree in Electrical and Electronics from HITEC University Taxila Cantt. Pakistan. He has over four and half years of practical experience in the development of high end embedded systems and artificial intelligence. Currently, He is Lecturer at University of Sargodha and also visiting researcher at Emwi-Tech. Ishfaq Hussain is also editor of multiple research publications in the field of embedded systems. He is also the recipient of a research grant by National ICT R&D Fund. His area of specialization is energy/performance optimization in reconfigurable MPSoC architectures



CISTER's main roles:
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Ishfaq Hussain
Speaker

S101 Auditorium/Seminar Room
1st Floor