6, Nov, 2018 10:00-11:15 (1 hour, 15 minutes)
PhD Thesis Defense - Cláudio MaiaScheduling parallel real-time tasks in multiprocessor platforms
In the past, increasing the frequency in single-core processors was enough to accommodate new software features. However, due to physical limitations, processor manufacturers stopped releasing single-core processors in favour of multicore ones. While this move is beneficial for the software industry overall, the use of Commercial-Off-The-Shelf (COTS) multicore platforms in real-time systems still remains a challenge.
Two main reasons can be identified for such a challenge. First, COTS multicore architectures are designed for average-case performance and resources, such as memory components (i.e., main memory, memory caches, etc.), peripherals, and buses, are shared among the cores. Consequently, if care is not taken, timing deviations, from the ones estimated at design time, may occur due to interference whenever different cores simultaneously access shared resources. Second, the platform not only supports concurrent execution at a core level but it also supports parallel execution at the platform level. Therefore, the major goal for the real-time systems community is to find efficient ways of dealing with the inherent parallel behaviour of the platform, and at the same time, be able to ensure application predictability by taking into account the shared resources in the platform. In this dissertation, this goal is divided into two distinct problems which are dealt independently from each other: (i) the problem of scheduling parallel real-time tasks in multiprocessor platforms; and (ii) the problem of sharing resources in multiprocessor platforms.
The first problem is covered from two different perspectives. In the first one, we focus on the response-time of synchronous parallel real-time tasks. The model under consideration targets tasks with fixed priorities, composed of several segments, each with an arbitrary number of parallel and independent units of execution that can be executed in parallel. To accomplish this we derive a worst-case scenario that allows one to compute the worst-case response-time of each task executing in the system. In the second perspective, a multi-stage approach is presented to analyse the schedulability of fork-join real-time tasks before and during runtime. That is, during runtime the work-stealing algorithm is used to reduce the average response-time of real-time tasks.
The second problem is addressed by considering a platform where the memory bus is shared among cores and, therefore, it is a source of interference whenever simultaneous memory requests are issued by the cores in the platform. To solve this problem, the 3-phase task model is used. First, an empirical analysis is performed where the performance of different priority assignment policies is compared against an implementation of global Earliest Deadline First (EDF) scheduling policy that considers inter-task interferences. Then, a schedulability test for the 3-phase task model is derived by taking into account the bus and task interferences.
President: Doutor José Alfredo Ribeiro da Silva Matos, Professor Catedrático da Faculdade de Engenharia da UPorto
Doutor Marko Bertogna, Professore Associato do Dipartimento di Scienze Fisiche, Informatiche e Matematiche da Universitá Degli Studi di Modena e Reggio Emilia, Itália;
Doutor António Casimiro Ferreira da Costa Professor Associado do Departamento de Informática da Faculdade de Ciências da ULisboa;
Doutor Luís Miguel Pinho de Almeida, Professor Associado do Departamento de Engenharia Eletrotécnica e de Computadores da Faculdade de Engenharia da U. Porto;
Doutor Mário Jorge Rodrigues de Sousa, Professor Auxiliar do Departamento de Engenharia Eletrotécnica e de Computadores da Faculdade de Engenharia da U. Porto
Supervisor: Doutor Luís Miguel Pinho Nogueira, Investigador CISTER – ISEP /IPP
Sala de Atos
Faculdade de Engenharia da Universidade do Porto
CISTER's main roles: