4, Sep, 2013 15:00-16:00 (1 hour)
CISTER, Porto, Portugal
Homepage: http://www-users.cs.york.ac.uk/~lsi/

ABSTRACT:
Many state-of-the-art approaches to power minimization in Networks-on-Chip (NoC) are based on the reduction of the communication paths taken by packets over the interconnect. This is often done by optimising the packet routing, the allocation of tasks that produce and consume those packets, or both. In all cases, the optimization affects the timeliness of the packets, because changes will occur in the way resources are shared at the platform cores (as tasks are reallocated) and NoC links (as packet routes are changed). In this talk, we will present optimization techniques that are able to minimize NoC power dissipation without sacrificing timing constraints, thus suitable to systems with hard real-time requirements. Our optimization engine is based on a Genetic Algorithm (GA) that evolves chromosomes representing the mapping of task to cores, guided by a multi-objective fitness function that combines power estimation macromodels and realtime schedulability analysis.

SHORT BIO:
Leandro Soares Indrusiak was born in 1974 in Santa Maria, RS, Brazil. He graduated in Electrical Engineering from the Federal University of Santa Maria (UFSM) in 1995 and obtained a MSc in Computer Science from the Federal University of Rio Grande do Sul (UFRGS), Porto Alegre, in 1998. He held a tenured assistant professorship at the Informatics department of the Catholic University of Rio Grande do Sul (PUCRS) in Uruguaiana from 1998 to 2000. His PhD research started in 2000 and extended his MSc work on design automation environments for microelectronic circuits. From 2001 to 2008 he worked as a researcher at the Technische Universität Darmstadt, Darmstadt, Germany, where he finished his PhD and then lead a research group on System-on-Chip design. His binational doctoral degree was jointly awarded by UFRGS and TU Darmstadt in 2003. Since October 2008, he is a permanent faculty member of University of York's Computer Science department (Lecturer 2008, Senior Lecturer 2013), and a member of the Real-Time Systems (RTS) research group. His current research interests include on-chip multiprocessor systems, distributed embedded systems, mapping and scheduling of applications over multiprocessor and distributed platforms, adaptive and reconfigurable computing. He currently supervises seven PhD students and one post-doc research assistant. He is the principal investigator of EPSRC-funded LowPowNoC and EU-funded DreamCloud projects, and a co-investigator in MCC and T-Crest projects. He is the coordinator of two MSc programmes (MSc in Computing and MSc in Information Technology), is a member of the university's Internationalization Steering Group and serves as the department's Internationalization Advisor.