Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures
Ref: CISTER-TR-180805 Publication Date: 11 to 14, Dec, 2018
Memory Feasibility Analysis of Parallel Tasks Running on Scratchpad-Based Architectures
Ref: CISTER-TR-180805 Publication Date: 11 to 14, Dec, 2018Abstract:
This work propose solutions for bounding the worst-case memory demand generated by parallel tasks running on multicore platforms with scratchpad memories. The objective is to propose a feasibility test that verifies whether the memories are large enough to contain the maximum memory backlog that may be generated by the system. Both closed-form bounds and more accurate algorithmic techniques are proposed. We show how one can use max-plus algebra and solutions to the max-flow cut problem to efficiently solve the memory feasibility problem. Experimental results are presented to evaluate the efficiency of the proposed feasibility analyses on synthetic workload and state-of-the-art benchmarks.
Daniel Casini
Geoffrey NelissenEvents:
Document:
View
Download39th IEEE Real-Time Systems Symposium (RTSS 2018), Session 9: Memory and I/O, pp 312-324.
Nashville, U.S.A..
DOI:10.1109/RTSS.2018.00047.
ISBN: 978-1-5386-7908-1.
ISSN: 2576-3172.
Notes: Best Presentation Award
Record Date: 29, Aug, 2018
Short links for this page: www.cister.isep.pt/docs/10_1109_rtss_2018_00047 www.cister.isep.pt/docs/cister_tr_180805 www.cister.isep.pt/docs/1398