Cache-aware Schedulability Analysis of PREM Compliant Tasks
Ref: CISTER-TR-220101 Publication Date: 2022
Cache-aware Schedulability Analysis of PREM Compliant Tasks
Ref: CISTER-TR-220101 Publication Date: 2022Abstract:
The Predictable Execution Model (PREM) is useful
for mitigating inter-core interference due to shared resources
such as the main memory. However, it is cache-agnostic, which
makes schedulabulity analysis pessimistic, via overestimation of
prefetches and write-backs. In response, we present cache-aware
schedulability analysis for PREM tasks on fixed-task-priority
partitioned multicores, that bounds the number of cache prefetches
and write-backs. Our approach identifies memory blocks loaded
in the execution of a previous scheduling interval of each task,
that remain in the cache until its next scheduling interval. Doing
so, greatly reduces the estimated prefetches and write backs. In
experimental evaluations, our analysis improves the schedulability
of PREM tasks by up to 55 percentage points
Syed Aftab Rashid
Muhammad Ali Awan
Pedro Souto
Konstantinos Bletsas
Eduardo TovarDocument:
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DownloadDesign, Automation and Test in Europe Conference (DATE 2022), Real-time, Dependable and Privacy-Enhanced Systems.
ANTWERP, Belgium.
Record Date: 11, Jan, 2022