A Parallel Programming Model for Ada
Ref: HURRAY-TR-110902 Publication Date: 6 to 10, Nov, 2011
A Parallel Programming Model for AdaRef: HURRAY-TR-110902 Publication Date: 6 to 10, Nov, 2011
Over the last three decades, computer architects have been able to achieve an increase in performance for single processors by, e.g., increasing clock speed, introducing cache memories and using instruction level parallelism. However, because of power consumption and heat dissipation constraints, this trend is going to cease. In recent times, hardware engineers have instead moved to new chip architectures with multiple processor cores on a single chip. With multi-core processors, applications can complete more total work than with one core alone.
To take advantage of multi-core processors, parallel programming models are proposed as promising solutions for more effectively using multi-core processors. This paper discusses some of the existent models and frameworks for parallel programming, leading to outline a draft parallel programming model for Ada.
ACM's Annual International Conference on Ada and Related Technologies Engineering Safe, Secure, and Reliable Software (SIGAda 2011), ACM New York, pp 19-26.
WOS ID: 000304072500010.