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July 2019

24, Jul, 2019

Fundamental Research Activities

KhronoSim Final Evaluation meeting in Coimbra

CISTER Researcher Cláudio Maia attended the final evaluation meeting for the KhronoSim project. In this meeting two evaluators assessed the project in terms of achieved objectives and results. After careful evaluation and discussion, the project was deemed a success as all the objectives for the project were achieved, resulting in the development of two demonstrators for the KhronoSim test platform: an automotive instrument cluster and a satellite.

In the project, among other tasks, the CISTER team was responsible for studying the state of the art of emulation for multicore systems and integrating the KhronoSim test platform with the selected emulator. The emulator selected for the project was QEMU, one of the most versatile emulators currently available in the market, on top of which CISTER developed the KhronoSim QEMU Module that allows one to instance, manage and control, via the KhronoSim platform, several QEMU instances.

 

4, Jul, 2019

Industry Collaborations

CISTER Researchers participated in TECH@PORTUGAL at Âlfandega do Porto

June 2019

18, Jun, 2019

Fundamental Research Activities

Distinguished Seminar on Communications for Satellites

11, Jun, 2019

Fundamental Research Activities

REASSURE progress meeting at U.Minho

On the 11th of June, CISTER Researchers David Pereira and Giann Nandi have participated in a progress meeting of REASSURE, that took place in the premises of the Department of Informatics of University of Minho.
The meeting, which counted also with the participation of REASSURE’s team members José Bacelar Almeida and Jorge Sousa Pinto from HASLab/ INESC TEC, had the purpose of analyzing the results obtained by both teams in this first year of REASSURE, and to plan the next steps for the second year of activities of the project, notably in what concerns the design of Domain Specific Languages and Cyber-Security Support in the design of runtime monitoring architectures.

Particular focus on the work developed by Giann, under his PhD studies, on the formal verification of WSN protocols using the ProVerif Tool, which is the core result described in the paper entitled “Security in Wireless Sensor Networks: A formal verification of protocols” that has been recently accepted in this year’s edition of INDIN 2019 – 17th IEEE International Conference on Industrial Informatics.

7, Jun, 2019

Fundamental Research Activities

Visit from Serbian Researcher of the RT-RK National Research Institute

7, Jun, 2019

Fundamental Research Activities

General Assembly and F2F meeting of the project SCOTT in Gdansk, Poland

6, Jun, 2019

Fundamental Research Activities

Periodic Seminar on "Effective System Integration"

May 2019

27, May, 2019

Fundamental Research Activities

Periodic Seminar on Thermal-Aware Scheduling

24, May, 2019

Industry Collaborations

THERMAC physical kick-off meeting at CISTER

21, May, 2019

Industry Collaborations

Portugal Space visit to Airbus Defence and Space (ADS)

21, May, 2019

Activities in the Academia

HDR examination of Luca Santinelli

Last 20th of May, at the ENSEEIHT in Toulouse, CISTER Vice-Director Luis Almeida participated in the HDR examination (Habilitation à Diriger de Recherche) of Luca Santinelli, a well-known member of the real-time systems community, based at ONERA, working essentially on probabilistic methods for the estimation of the worst-case execution and response times.
The examination focused on the research path of the candidate and his research perspectives for the future.
Beyond Luis Almeida, the examination committee included Alan Burns U.York,UK; Isabelle Puaut, U.Rennes, FR; Laurent George, ECE, FR; Yves Sorel, INRIA, FR; Joel Goossens, ULB, BE and Christian Fraboul, U.Toulouse, FR.
 

19, May, 2019

Fundamental Research Activities

Another Successful Industry-Driven Project delivered

17, May, 2019

Fundamental Research Activities

Final Event of the ENABLE-S3 project in Graz, Austria

8, May, 2019

Industry Collaborations

VORTEX General Assembly

The first VORTEX General Assembly was held at the CISTER Labs on the 8th of May, alongside with VORTEX Bootcamp.
This first General Assembly was mainly to ratify changes in the association bylaws proposed by the supervisory board, to name the members of the assembly and elect members of the VORTEX Scientific Council.
After discussing the overall charter and proposed changes, the assembly approved by unamity those changes.
The General Assembly is thus constituted by Jaime Medeiros - President (Altran/CRALaw); Nuno Correia - Secretary (NOVALINCS/UNL) and Paulo Gandra de Sousa - Secretary (CISTER/ISEP).
CISTER Researchers David Pereira and Ricardo Severino were appointed as members of the VORTEX Scientific Council and Eduardo Tovar was appointed as President of the VORTEX Scientific Council.
After this formality, the assembly members discussed about the future of the association based on the briefing of the bootcamp.

7, May, 2019

Industry Collaborations

VORTEX Bootcamp in CISTER

April 2019

23, Apr, 2019

Fundamental Research Activities

Periodic Seminar on Security in Embedded Systems

23, Apr, 2019

Activities in the Academia

Open Debate Session about "Plasticology" at Porto Design Factory

11, Apr, 2019

Fundamental Research Activities

Periodic Seminar on "the Interaction-Centric Paradigm"

1, Apr, 2019

Fundamental Research Activities

Distinguished seminar on Model-Driven Engineering

March 2019

29, Mar, 2019

Industry Collaborations

VORTEX, the Collaborative Laboratory in CPS, was officially launched

27, Mar, 2019

Fundamental Research Activities

+Science +Europe

21, Mar, 2019

Activities in the Academia

A Machine Learning challenge was won by CISTER interns

19, Mar, 2019

Fundamental Research Activities

PhD student from Universidad de Alcalá invited to give a talk on "Digital Communications for the Control of Modular Multilevel Converters" at CISTER

Tomás Corrêa gave a talk on “Digital Communications for the Control of Modular Multilevel Converters” on the 19th of March, at CISTER/FEUP. Tomás is a PhD student at the Universidad de Alcalá de Henares in Spain and started by explaining the concept of Modular Multilevel Converter (MMC) and how it impacted the conversion and control of electrical energy at high voltage levels. MMCs, invented in 2001, are composed of a potentially large number of power modules, as known as cells, that are stacked and switched on and off individually to generate a voltage wave with a desired shape, typically sinusoidal. The cells are controlled centrally but individual connections to the controller can limit scalability and hinder MMCs applicability. Thus, Tomas focused on the current trend toward using digital communications in MMCs and told us about the benefits and challenges this trend implies, particularly concerning the trade-off between latency, reliability and cost. Among different alternatives, Ethernet technology connected in a ring topology stands up, currently, as the best compromise essentially due to the high reliability-cost ratio and despite the relatively high latency it implies. Tomas shared with us, then, his research on Ethernet-based ring networks to bring latency to a minimum, designing specific protocols, namely TTRing and DiSortNet, for specific distributions of the MMC control, that reduce by one half the best latency achievable with current COTS technology, supporting 400 nodes with cycle times below 200us.

PHOTOS:
At CISTER's Facebook Page / At CISTER's Instagram Page

12, Mar, 2019

Fundamental Research Activities

Training on "Introduction to Real-time Systems"at CISTER Facilities

8, Mar, 2019

Fundamental Research Activities

CISTER Researchers attended the seminar on "Analysis, Design, and Control of Predictable Interconnected Systems"

7, Mar, 2019

Fundamental Research Activities

Pedro Miguel Santos gave a talk on Vehicular Networking and Urban Sensing Platforms

1, Mar, 2019

Fundamental Research Activities

Two new PhD members recently joined CISTER

February 2019

21, Feb, 2019

Fundamental Research Activities

Scientific Council Meeting

12, Feb, 2019

Activities in the Academia

Computer Science department delivers Best Student Awards

11, Feb, 2019

Fundamental Research Activities

CISTER Researchers participated in the Flexigy Workshop, in Coimbra

FLEXIGY project aims at creating a Virtual Energy Community concept that will operate “behind the meters” – i.e. the development of flexibility management services to allow energy aggregators to involve energy resources with private bilateral contracts, thus enabling the use of distributed energy resources in a collaborative way, with significantly larger community benefits when compared to individual optimization, supported by a cyber-physical infrastructure required to support load flexibility management with community-wide optimization mechanisms (which includes storage management, production management and load management), thus ensuring the security and satisfaction levels for the economic viability of the proposed solution. In this project energy transactions will be based on the blockchain concept and virtual currencies, in order to increase trust and end-user engagement.
In this meeting Luis Lino Ferreira and Rafael Rocha presented their work on the Flex Offer concept and discussed with the other partners the architecture for the system.
 

7, Feb, 2019

Fundamental Research Activities

CISTER Researcher attended the F2F technical board meeting of the project SCOTT

Ramiro Robles represented CISTER/ISEP in the F2F technical board meeting of the project SCOTT held at the premises of our partner NXP in Munich, Germany on the 7th of February 2019.
This meeting was mainly focused on how the different WPs and Technology lines of the project will answer the comments of the reviewers provided in the official feedback after the first year of the project. In addition, the meeting was also focused on refining the impact and exploitation definition of the project highlighting the main measurable outcomes expected of the project and how we will achieve the target values.
CISTER/ISEP acted as the chair of the technical board, leader of the reference architecture of the project and representative of the aeronautics domain.

 

1, Feb, 2019

Fundamental Research Activities

CISTER participated in Portuguese delegation led by Minister Manuel Heitor at Carnegie Mellon University (CMU)

January 2019

31, Jan, 2019

Fundamental Research Activities

CISTER leads new longer-term contracts with researchers

31, Jan, 2019

Fundamental Research Activities

Four new PhD students have joined CISTER

During the last month four new PhD students joined CISTER.

Hajar and Amir from Iran, Ênio from Brasil and Jingjing from China, are already aiming their brain power at the next three years, in which they will be doing research in topics such as reliable 5G communications, cooperative autonomous control, and multiprocessor platforms for embedded safety critical systems.

Hajar Baghcheband was born in Shiraz, Iran. She received the B.Sc. in computer software engineering from IAU of Shiraz and the M.Sc. degrees in the field of Information Technology from Graduate University of Advanced Technology (GUAT). Her master thesis was granted by Iran Telecommunications Research Center (ITRC) and focused on applying data mining techniques to intrusion detection system. Since 2009, she was lecturer at higher education institutes and colleges of Shiraz.
In 2016, her new role in company as project management and database administrator started which their project shortlisted for World Summit Award.
Since September 2018, Hajar started to pursue her education toward PhD in Computer Engineering at the Faculty of Engineering of the University of Porto. Her research interests are Machine Learning, Multi agent System, Artificial Intelligence, Data mining, Business Intelligence, Decision Support system and Database.

Amir Hossein Farzamiyan was born in Shiraz, Iran, in 1985. He received both the B.Sc. and the M.Sc. degrees in the field of Electrical and Electronic engineering. He is a graduate with strong communication and organizational skills gained in his study, research and work experience in communication networks and Wireless Communication, now seeking to pursue his study toward PhD in the field of telecommunication.
His research interests are Wireless (Radio) Access Networks, 5G Networks, Internet of Things, Software Defined Network, Advanced Wireless Communications, Cyber-Security, Network Packet Routing Protocol, Network Topology.

Ênio Filho was born in 1984 in Brazil. He has a BSc degree in Automation and Control (2006) and a MSc degree in Mechatronics Systems (2012) both from Universidade de Brásilia (UnB). He is an assistant professor at Instituto Federal de Goiás (IFG), in Brazil.
He is pursuing a PhD in Electrical and Computer Engineering at the Faculty of Engineering of the University of Porto (PDEEC).His biggests interests are in autonomous vehicles, communication networks and artificial intelligence in real time applications.

Jingjing Zheng was born in 1991 in Hubei, China. From a very young age he showed enormously passionate about computers and mathematics. During his college years, he participated in China Undergraduate Mathematical Contest in Modeling three times, and obtained the Second Prize in Jiangxi Province, the First Prize in Jiangxi Province, the Second Prize in the Nation, respectively.
In 2015 he began to study Control Science and Engineering at the Guangdong University of Technology, where he had done the master thesis of Research on Resource Allocation and Multi-agent Co-optimization for Dynamic Heterogeneous Multi-core Processors, and having obtained a good result through peer reviews. After, he received the M.S.degree from Guangdong University of Technology, China, in June 2018.
Currently his research interests are in Real Time Embedded Systems, Multi-core processors and Optimization Algorithm.
 

30, Jan, 2019

Industry Collaborations

Participation in new CPS CoLab meeting in Lisbon

26, Jan, 2019

Activities in the Academia

CISTER Junior Researcher: Talk A Bit 2019

24, Jan, 2019

Achievements in Academia

José Fonseca successfully defended his PhD thesis at FEUP

21, Jan, 2019

Fundamental Research Activities

Distinguished Seminars by Scientists from University of York and from Politecnico di Milano

Robert I. Davis gave a distinguished seminar on "Transferring Real-Time Systems Research into Industrial Practice"
During this talk, Dr Robert I. Davis discussed two impact case studies where real-time systems research has been successfully transferred into industrial practice. In each case, the technology created was translated into viable commercial products and led to significant advances in the automotive electronics and avionics domains, providing substantial returns on investment for the companies using the technology.

Robert I. Davis is a Reader in the Real-Time Systems Research Group at the University of York, UK. Robert received his PhD in Computer Science from the University of York in 1995. Since then he has founded three start-up companies, all of which have succeeded in transferring real-time systems research into commercial products. Robert’s research interests include the following aspects of real-time systems: scheduling algorithms and analysis for single processor, multiprocessor and networked systems; analysis of cache related pre-emption delays, mixed criticality systems, and probabilistic hard real-time systems.

PHOTOS:
At CISTER's Facebook Page / At CISTER's Instagram Page

Stefano Zanero from Politecnico Di Milano presented a talk on “Breaking the Laws of Robotics: Attacking Industrial Robots”, where he discussed vulnerabilities of industrial robots and the work achieved by his research group to address potential attacks. Stefano presented a recent attack performed by his students to alter the precision of an industrial robot which can lead to potential harm to products and even users. Various use cases were discussed including an attack via insecure web interfaces, weak authentication protocols, exposure of industrial routers, etc. The impact of existing domain specific languages in this area was also discussed during this talk. More information around this work is available at robosec.org.

Stefano Zanero received a PhD in Computer Engineering from Politecnico di Milano, where he is currently an associate professor. His research focuses on malware analysis, cyberphysical security, and cybersecurity in general. Besides teaching "Computer Security" and "Computer Forensics" at Politecnico, he has an extensive speaking and training experience in Italy and abroad. He co-authored over 70 scientific papers and books. He is a Senior Member of the IEEE (for which he sits on the MGA board), the IEEE Computer Society (for which he is a member of the Board of Governors), and a lifetime senior member of the ACM. Stefano co-founded the Italian chapter of ISSA (Information System Security Association). He has been named a Fellow of ISSA and sits in its International Board of Directors. Stefano is also a co-founder and chairman of Secure Network, a leading information security consulting firm based in Milan and in London; a co-founder of 18Months, a cloud-based ticketing solutions provider; and a co-founder of BankSealer, a startup in the FinTech sector that addresses fraud detection through machine learning techniques.

PHOTOS:
At CISTER's Facebook Page / At CISTER's Instagram Page

21, Jan, 2019

Fundamental Research Activities

Giann Nandi gave a talk on Formal Verification of Cryptographic Protocols

16, Jan, 2019

Fundamental Research Activities

CISTER Researchers partipated on ECS Brokerage event, in Brussels

December 2018

14, Dec, 2018

Fundamental Research Activities

CISTER has great participation in RTSS 2018

11, Dec, 2018

Fundamental Research Activities

CISTER Researcher participated in the last General Assembly of ENABLE-S3 project

November 2018

28, Nov, 2018

Achievements in Academia

Journal Paper on "Uneven memory regulation for scheduling IMA applications on multi-core platforms" published

CISTER Researchers Ali Awan, Pedro Souto, Benny Åkesson, Konstantinos Bletsas and Eduardo Tovar have published the journal paper on "Uneven memory regulation for scheduling IMA applications on multi-core platforms".
It considers a scheduling arrangement with partitioned ser vers and memory access regulation, and its schedulability analysis. The main novelty over the state-of-the-art is that the servers use EDF and the periodic memory access budgets are uneven in the general case and defined on a per-server basis (rather than per-core).
 

22, Nov, 2018

Fundamental Research Activities

CISTER Researchers participated on EFECS 2018, in Lisbon

CISTER Researchers Eduardo Tovar, Luis Lino Ferreira and Ricardo Severino, attended EFECS 2018, that took place at the Lisbon Congress Centre - CCL .

EFECS 2018 is an international forum with a focus on 'Our Digital Future' along the Electronic Components and Systems value chain in Europe.
The organisers of this event, AENEAS, ARTEMIS-IA, EPoSS, ECSEL Joint Undertaking and the European Commission, in association with EUREKA, have joined forces to provide numerous opportunities to learn more about the latest developments, cooperation and funding possibilities in the ECS Community.
Several projects with CISTER participation were presented in the event, in the form of posters or in the form a small pitches. Additionally, CISTER members participated in several consortium building meetings, which will target the next Eureka and ECSEL calls.

Ongoing ECSEL Projects at CISTER:
Productive 4.0
SCOTT
ENABLE-S3
SafeCOP


21, Nov, 2018

Fundamental Research Activities

Cláudio Maia, participated in the 5th edition of "AED Days", in Oeiras

15, Nov, 2018

Fundamental Research Activities

Sanjay K. Jha gave a CISTER distinguished seminar on Security in Internet of Things (IoT)

6, Nov, 2018

Achievements in Academia

Cláudio Maia successfully defended his PhD thesis at FEUP

October 2018

18, Oct, 2018

Industry Collaborations

Ramiro Robles participated in the SCOTT General Assembly

From the 16th until the 18th of October, 2018, the SCOTT project consortium gathered in the city of Cork Ireland for a face-to-face and general assembly meetings. This is the third GA of the project and the second in 2018. This meeting was mainly used to keep track of the progress and to analyze the feedback from the reviewers after the meeting in Brussels in September 2018. CISTER/ISEP plays a key role in the project as leader of the technology line of the reference architecture, chair of the technical board, and co-lead of the aeronautics use case. SCOTT aims to build trust in IoT solutions for 5 different industrial domains: aeronautics, automotive, railway, building, and healthcare. SCOTT uses the concept of the Bubble to enhanced backwards compatibility with existing domain infrastructure, encapsulating these underlying technologies with a modern IoT interoperable and cross-domain cloud application environment with enhanced security, safety and trust.

15, Oct, 2018

Fundamental Research Activities

Kai Li nominated as Associate Editor for IEEE Access Journal

CISTER researcher Kai Li nominated as Associate Editor for IEEE Access Journal. As the Associate Editor, Kai Li is responsible for ensuring that the publication maintains the highest quality while adhering to the publication policies and procedures of the IEEE. He will also help facilitate a rapid review process that takes less than two weeks, and coordinate the careful and critical review. His research interests include vehicular communications and security, resource allocation optimization, Cyber-Physical Systems, Internet of Things, human sensing systems, sensor networks and UAV networks.