Work-In-Progress: WCRT Analysis for the 3-Phase Task Model in Partitioned Scheduling
Ref: CISTER-TR-201005 Publication Date: 1 to 4, Dec, 2020
Work-In-Progress: WCRT Analysis for the 3-Phase Task Model in Partitioned SchedulingRef: CISTER-TR-201005 Publication Date: 1 to 4, Dec, 2020
Multicore platforms are being increasingly adopted in Cyber-Physical Systems (CPS) due to their advantages over single-core processors, such as raw computing power and energy efficiency. Typically, multicore platforms use a shared system bus that connects the cores to the memory hierarchy (including caches and main memory). However, such hierarchy causes tasks running on different cores to compete for access to the shared system bus whenever data reads or writes need to be made. Such competition is problematic as it may cause large variations in the execution time of tasks in a non-deterministic way. This paper presents an analysis that allows one to derive bus contention aware worst-case response-time of tasks that follow the 3-phase task model executing under partitioned scheduling.
41st IEEE Real-Time Systems Symposium (RTSS 2020), WiP.