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Timing Analysis of an Embedded Architecture for a Real-Time Power Line Communications Network
Ref: HURRAY-TR-090301       Publication Date: 23, Mar, 2009

Timing Analysis of an Embedded Architecture for a Real-Time Power Line Communications Network

Ref: HURRAY-TR-090301       Publication Date: 23, Mar, 2009

Abstract:
Although voice and data transmission over power-lines is not a recent technology, the use of this medium to support time-constrained communications is still a subject of research. In the scope of an European R&D project (REMPLI - Real-time Energy Management via Powerlines and Internet) a new communication architecture was proposed, based on a two-level hierarchic system (medium-voltage and low-voltage). In order to support the required network previsibility and efficiency requirements, one of the project partners developed a new embedded architecture based on the Hyperstone’s processor HyNet32XS interfacing with a power-line chipset (DLC-2C). The uClinux operating system was ported for this architecture to support the development of the new software architecture. Due to the architecture characteristics and the (multi)master/slave behaviour of the medium access layer, new packet routing and scheduling protocols – fundamental for the correct functioning of the network – were specified. In this context, the main objective of this dissertation is to study the timing behaviour of this architecture, focusing in the behaviour of the routing and scheduling protocols. Particularly important is the validation of the timing behaviour of these new protocols.
Keywords: Real-time networks, embedded systems, embedded Linux, power-line communications.

Authors:
António Barros


Master Thesis, Faculdade de Engenharia da Universidade do Porto.
Porto, Portugal.



Record Date: 23, Mar, 2009