Mixed-criticality scheduling with memory regulation
Ref: CISTER-TR-160604 Publication Date: 5 to 8, Jul, 2016
Mixed-criticality scheduling with memory regulationRef: CISTER-TR-160604 Publication Date: 5 to 8, Jul, 2016
The state-of-the-art models and schedulability analysis for mixed-criticality multicore systems overlook low-level aspects of the system. To improve their credibility, we therefore incorprate, in this work, the effects of delays from memory contention on a shared bus. Specifically, to that end, we adopt the predictable memory reservation mechanism proposed by the Single Core Equivalence framework. Additionally, we explore how the reclamation, for higher-criticality tasks, of cache resources allocated to lower-criticality tasks, whenever there is a criticality (mode) change in the system, can improve schedulability.
28th Euromicro Conference on Real-Time Systems (ECRTS 2016), WiP.