HopliteRT*: Real-Time NoC for FPGA
Ref: CISTER-TR-200803 Publication Date: 20 to 25, Sep, 2020
HopliteRT*: Real-Time NoC for FPGARef: CISTER-TR-200803 Publication Date: 20 to 25, Sep, 2020
With the increasing number of computation nodes integrated in multi- and many-core platforms, network-on-chips (NoCs) emerged as a new communication medium in systemson- chips (SoCs). HopliteRT is a new NoC design that was recently proposed to address the needs of real time systems whilst respecting the constraints of FPGA platforms. In this work, we (1) introduce priority-based routing in HopliteRT, (2) change the network topology in order to improve the packets’ worst-case traversal time (WCTT), (3) identify a flaw in the existing timing analysis of HopliteRT, and (4) develop a new timing analysis that is proven correct. We also show by means of experiments that the modifications of HopliteRT proposed in this paper allows for at least 2x improvement on the worst and average case traversal time of high priority packets, without impacting the quality of service of low-priority packets. The timing properties of high priority flows are greatly improved for negligible additional hardware cost. The proposed NoC has been implemented in Verilog and synthesized for a Xilinx Virtex-7 FPGA platform.
ACM SIGBED International Conference on Embedded Software (EMSOFT 2020).
Notes: EMSOFT 2020 is SIGBED's flagship conference and part of the Embedded Systems Week (ESWEEK).