Cache Persistence-Aware Memory Bus Contention Analysis for Multicore Systems
Ref: CISTER-TR-191102 Publication Date: 9 to 13, Mar, 2020
Cache Persistence-Aware Memory Bus Contention Analysis for Multicore SystemsRef: CISTER-TR-191102 Publication Date: 9 to 13, Mar, 2020
Memory bus contention strongly relates to the number of main memory requests generated by tasks running on different cores of a multicore platform, which, in turn, depends on the content of the cache memories during the execution of those tasks. Recent works have shown that due to cache persistence the memory access demand of multiple jobs of a task may not always be equal to its worst-case memory access demand in isolation. Analysis of the variable memory access demand of tasks due to cache persistence leads to significantly tighter worst-case response time (WCRT) of tasks. In this work, we show how the notion of cache persistence can be extended from single-core to multicore systems. In particular, we focus on analyzing the impact of cache persistence on the memory bus contention suffered by tasks executing on a multicore platform considering both work conserving and non-work conserving bus arbitration policies. Experimental evaluation shows that cache persistence-aware analyses of bus arbitration policies increase the number of task sets deemed schedulable by up to 70 percentage points in comparison to their respective counterparts that do not account for cache persistence.
Design, Automation and Test in Europe Conference (DATE 2020), pp 442-447.