An Efficient Proactive Thermal-Aware Scheduler for DVFS-enabled Single-Core Processors
Ref: CISTER-TR-210301 Publication Date: 7 to 9, Apr, 2021
An Efficient Proactive Thermal-Aware Scheduler for DVFS-enabled Single-Core ProcessorsRef: CISTER-TR-210301 Publication Date: 7 to 9, Apr, 2021
For decades now, thermal rise has been spotted as one of the major constraints of performance for high-end safety-critical processors. In this context, Dynamic Voltage and Frequency Scaling (DVFS) based solutions have proven to be effective to manage the chip temperature. In this paper, we consider the scheduling problem of non-preemptive periodic tasks on a single-core processor with DVFS-enabled capabilities under thermal-aware design. We assume that the tasks are scheduled by following any Fixed-Task-Priority (FTP) scheduler such as the traditional Rate Monotonic (RM) and Deadline Monotonic (DM). Then, we propose a new scheduling scheme, referred to as NP-COIN, which makes it possible to control both the processor activity and the triggering of the cooling mechanism with as little impact on performance as possible. We provide a thorough theoretical analysis of our solution, in terms of average temperature gain and timing penalty, against the classical DVFS schedule. Finally, we validate our theoretical results and assess the performance of our solution through a real-world use-case study from the avionics domain and through intensive simulations by using synthetic test cases.
29th International Conference on Real-Time Networks and Systems (RTNS 2021), Session 3: Scheduling and Timing analysis.