Page History: CISTER Seminar Series

September 9 - Kostiantyn Berezovskyi, ISEP, Portugal- Makespan computation of threads executing on a GPU¶

Talk abstract:Originally graphics processors were developed for rendering graphics, but during the last decade they evolved towards being architecture for general-purpose computations. Also they are expected to become important parts of embedded systems hardware not only for graphics. For such usage, we need real-time schedulability analysis for General-Purpose Graphics Processor Units (GPGPUs), that differs from classical one in the scientific discipline of real-time systems. A significant difference between these two analyses is that for GPGPU the execution of one thread may require hardware units which are shared among other threads. We develop a simple method for finding pessimistic makespan of threads. The threads are competing for resources of a single streaming multiprocessor (SM) of hardware architecture based on NVIDIA Fermi, that satisfies some assumptions that were made to simplify the analysis. We implemented this method in a cross-platform application that generates Integer Linear Programming (ILP) problem, launches the proprietary ILP-solver and creates schedule of utilizing SM`s resources according to the solution of that problem.

Speakers Bio: Kostiantyn Berezovskyi holds M.Sc. degree from Taras Shevchenko National University of Kyiv. At university he paid great attention to software development and have gathered experience in parallel programming. Now he is a PhD student at CISTER. His interests are related to the schedulability analysis of general purpose graphics processor units.